Study of Existing Full Adders and To Design a LPFA (Low Power Full Adder)

This paper describes the different logic style used for CMOS full adders and different equation used to implement the required Boolean logic for full adders. This paper also describes that the speed of the design is limited by size of the transistors, parasitic capacitance and delay in the critical path. Power consumption and speed are two important but conflicting design aspects; hence a better metric to evaluate circuit performance is power delay product (PDP).The driving capability of a full adder is very important, because, full adders are mostly used in cascade configuration, where the output of one provides the input for other. If the full adders lack Driving capability then it requires additional buffer, which consequently increases the power dissipation. At last a new LPFA Design is proposed with comparisons between the various full adders to show the better performance of LPFA in terms of power consumption, area (number of transistors) and delay. The LPFA and all other various full adders are designed and simulated using mentor graphics tool in 0.18 μm technology. The frequency used is 100 MHz. the voltage and all the various full adders and others designs are simulated at a voltage supply of 1.8V at same frequency.